JNTU B.Tech ECE-Computer Organization Exam Previous Year Papers

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1. (a) Discuss about Flynn’s classification of computers.
(b) Explain about communication topologies used in multiprocessors. [16]

2. Write about direct, indirect, register direct, register indirect, immediate, implicit,
relative, index, and base address mode of addressing. Why do we need so many
addressing modes? Is the instruction size influenced by the number of addressing
modes which a processor supports? State whether the number of addressing modes
will be more in RISC or CISC? [16]

3. (a) Why do we need subroutine register in a control unit? Explain. [8]
(b) Explain nanoinstructions and nanometry. Why do we them? [8]

4. Explain the computational errors. Why do they occur?. Give some problems where
these errors are catastrophic. Also, give some practical examples (algorithms) where
error gets
(a) accumulated and
(b) multiplies. [16]

5. Explain the following with applications for each:
(a) ROM
(b) PROM
(c) EPROM
(d) EEPROM. [4+4+4+4]

6. Explain the following:
(a) Isolated Vs Memory mapped I/O
(b) I/O Bus Vs Memory Bus
(c) I/O Interface
(d) Peripheral Devices. [4+4+4+4]

7. (a) What is pipelining? Explain. [8]
(b) Explain four segment pipelining. [8]



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JNTU B.Tech ECE-Computer Organization exam paper 1
1. Describe all optional PCI signal lines with designation and type. [16]
2. Discuss about the IEEE standard for binary °oating point arithmetic [16]
3. NOOP instruction has no e®ect on the CPU state other than incrementing the program counter.
Suggest some uses of this instruction with examples.
[16]
4. (a) List and describe di®erent Motorola 88000 bit-¯eld instructions.
(b) Discuss about register management in Motorola 88000 [8+8]
5. (a) Explain di®erent techniques of cache mapping function
(b) what are the merits and demerits of each. [10+6]
6. (a) Discuss about possible DMA con¯gurations.
(b) What is vectored interrupts.
(c) Discuss about 68000 interrupt structure. [6+4+6]
7. (a) Di®erentiate between impact and non-impact printers.
(b) Elaborate on mechanical printers.
(c) Discuss about joysticks which use potentiometers as position transducers.
[5+5+6]
8. (a) Discuss about exeception in multiple execution unit pipelined processors with examples.
(b) Discuss about dispatch and superscalar operation in multiple execution unit pipelined processors
[8+8]

JNTU B.Tech ECE-Computer Organization exam paper 2
1. (a) Find the actual number from its IEEE 754 representation.
Sign = 0
Exponent = 1000 0000
Mantissa = 1100 0000 0000 0000 0000 000 [6]
(b) What is meant by normalization in °oating point representation? Why do we need it? What is
bias? What normalization is used in IEEE 754 standard? [10]
2. Design register selection circuit to select one of the four 4-bit registers content on to bus. Give fuller
explanation. [16]
3. (a) What are the design goals for a designer while deciding a hardwired or microprogrammed CU for
a CPU. [8]
(b) Explain nanoinstructions and nanometry. Why do we need them. [8]
4. (a) How many bits are needed to store the result addition, subtraction, multiplication and division
of two n-bit unsigned numbers. Prove. [8]
(b) What is over°ow and under°ow. What is the reason?. If the computer is considered as in¯nite
system do we still have these problems?. [8]
5. (a) What is the functioning of a Flash Memory? Explain. [8]
(b) Give the detailed picture of Memory Hierarchy. [8]
6. (a) What are the di®erent types of I/O communication techniques? Give brief notes.
(b) In the above techniques, which is the most e±cient? Justify your answer. [8+8]
7. Explain the following with related to the Instruction Pipeline
(a) Pipeline con°icts
(b) Data dependency
(c) Hardware interlocks
(d) Operand forwarding
(e) Delayed load
(f) Pre-fetch target instruction
(g) Branch target bu®er
(h) Delayed branch [8£2=16]
8. (a) What is the functioning of cross bar switch network? Explain. With a neat sketch
[12]
(b) How many switch points are there in a cross bar switch network that connect 'p' Processors to
'm' Memory modules. [4]

Here is the exam syllabus of JNTU ECE Computer Organization.

UNIT - I:
Basic Structure of Computers: Computer Types, Functional UNIT, Basic Operational Concepts, Bus, Structures, Software, Performance, Multiprocessors and Multi Computers, Data Representation, Fixed Point Representation, Floating - Point Representation.
Register Transfer Language and Micro Operations: Register Transfer Language, Register Transfer Bus and Memory Transfers, Arithmetic Micro Operations, Logic Micro Operations, Shift Micro Operations, Arithmetic Logic Shift Unit, Instruction Codes, Computer Registers Computer Instructions - Instruction Cycle.
Memory - Reference Instructions, Input - Output and Interrupt, STACK Organization, Instruction Formats, Addressing Modes, DATA Transfer and Manipulation, Program Control, Reduced Instruction Set Computer.
UNIT - II:
Micro Programmed Control: Control Memory, Address Sequencing, Microprogram Examples, Design of Control Unit, Hard Wired Control, Microprogrammed Control.
The Memory System: Basic Concepts of Semiconductor RAM Memories, Read-Only Memories, Cache Memories Performance Considerations, Virtual Memories secondary Storage, Introduction to RAID.
UNIT - III:
Input-Output Organization: Peripheral Devices, Input-Output Interface, Asynchronous Data Transfer Modes, Priority Interrupt, Direct Memory Access, Input-Output Processor (IOP), Serial Communication; Introduction to Peripheral Components, Interconnect (PCI) Bus, Introduction to Standard Serial Communication Protocols like RS232, USB, IEEE1394.
UNIT - IV:
Operating Systems Overview: Overview of Computer Operating Systems Functions, Protection and Security, Distributed Systems, Special Purpose Systems, Operating Systems Structures-Operating System Services and Systems Calls, System Programs, Operating System Generation.
Memory Management: Swapping, Contiguous Memory Allocation, Paging, Structure of the Page Table, Segmentation, Virtual Memmory, Demand Paging, Page-Replcement Algorithms, Allocation of Frames, Thrashing Case Studies - UNIX, Linux, Windows
Principles of Deadlock: System Model, Deadlock Characterization, Deadlock Prevention, Detection and Avoidance, Recovery from Deadlock.
UNIT - V:
File System Interface: The Concept of a File, Access Methods, Directory Structure, File System Mounting, File Sharing, Protection.
File System Implementation: File System Structure, File system Implementation, Directory Implementation, Allocation Methods, Free-Space Management.

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