JNTU, B.Tech In Computer Science and Engineering Digital Logic Design previous years

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JNTU, B.Tech In Computer Science and Engineering Digital Logic Design previous years question papers






Contact Details:
Jawaharlal Nehru Technological University
Main Road,
Kukatpally Housing Board Colony,
Kukatpally,
Hyderabad,
Andhra Pradesh 500085 ‎
040 2315 8661
India

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JNTU, B.Tech In Computer Science and Engineering Digital Logic Design previous years question pa.pdf (30.0 KB, 44 views)

The JawaharLal Technical University (JNTU), B.Tech (Computer Science and Engineering)’s subject Digital Logic Design paper carry 80 marks. The exam is for 3 hours. Students need to do any five questions.

As per your requirement, I am giving you JNTU Digital Logic Design 2008 paper.

Convert the following to Decimal and then to Hexadecimal.
(a) 12348
(b) 12678
(c) 11001111 2
(d) 110111012
(e) 78610
(f) 55510

A sequential circuit with 3 D-flip-flops A, B and C has only one input ‘X’ and one
output ‘X’ with following relationship
DA = B⊕ C ⊕ X,
DB = A,
DC = B
(a) Draw the logic diagram of the circuit.
(b) Obtain logic diagram, state table and state diagram.

Draw and explain 4-bit universal shift register.

Explain different types of shift re

Describe the operation of the SR Latch using NAND gate with the help of
truth table, transition table and the circuit.

Explain the operation and use of De bounce

Draw and explain the block diagram of PAL.

Implement the following Boolean functions using PAL.
w(A,B,C,D) = Σ m (0,2,6,7,8,9,12,13)
x (A,B,C,D) = Σ m (0,2,6,7,8,9,12,13,14)
y (A,B,C,D) = Σ m (2,3,8,9,10,12,13)
z (A,B,C,D) = Σ m (1,3,4,6,9,

JNTU, B.Tech (Computer Science and Engineering)’s subject Digital Logic Design paper

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Answered By StudyChaCha Member

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