HDL Lab Viva Questions Vtu

Hello sir, is there any one can provide me some questions for HDL lab for viva question in VTU?

The Hardware description language is any language from a class of computer languages and/or programming languages for formal description of electronic circuits, and more specifically, digital logic is taught at VTU.

It can describe the circuit's operation, its design and organization, and tests to verify its operation by means of simulation.

Some HDL lad Viva questions of VTU:

Expand VHDL.What is the difference between VHDL and Verilog?
What is the difference between (i) signal and variable (ii) generic & Parameter (iii) function & procedure (iv) task & function (v) always & initial (vi) register & variable (vii) signal & wire
What are the different styles of models in VHDL and Verilog?
What are the operators in VHDL & Verilog?
Which is an operator is having most priority?
What is meant by sensitivity list?
Give the Following syntax in HDL (i) if, for, function, procedure (ii) while, case.
What is the operating frequencyof your FPGA?
Expand FPGA & ASICWhat are the data types in VHDL?
What are the data types in Verilog?What is delta time?
What is the difference between ( 0 to 3) & ( 3 downto 0)?
Write the truth table & Excitation table for D filp flop, SR , T, JK
What are the file operations in Verilog?
What is meant by synthesis?
Write the flow chart for synthesis process?
What is the difference between combination circuit & sequential circuit?
What is the difference between latch & Flip flop?Write a Verilog code to swap contents of two registers with and without a temporary register?
In a pure combinational circuit is it necessary to mention all the inputs in sensitivity list? If yes, why?What is the difference between wire and reg?
Give only two xor gates one must function as buffer and another as not gate?
Build a 4:1 mux using only 2:1 mux?What are shift operators in HDL?
What are the logical operators in VHDL & Verilog?
What is the gate density of your FPGA?
What is data flow model, structural model, behavioral model?How you invoke from VHDL to Verilog and vice versa?
What is the difference between SR flip flop & JK flip flop?
What is the difference between synchronous reset & Asynchronous reset?
What is the difference between stepper motor & DC motor?
What is the step size of stepper motor?
What is mux and demux?
What is encoder and decoder?
What is the difference between encoder & priority encoder?
What is binding?
What is the difference between “bit” and “std_logic”?
What are the std_logic values?
What are the different types of buffers are in Verilog HDL?
What is the difference between dc motor and stepper motor?
What are the applications of dc motor and stepper motor?
Write the syntax for casex and casez.What is screen time?
Draw the simulation waveform for D-latch using signal assignment and variable assignment statements inside the process.
What is SRAM?
What is mealy model and Moore model?
What are user defined types?
What are the packages are available in VHDL? And also give the syntax for package
How to call procedure and function within the process?
Give the syntax for arrays in VHDL and Verilog.
What are the VHDL files processing?