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February 18th, 2014 03:59 PM
Re: GATE Questions on Digital Logic

As per your request, here I am sharing the GATE Digital Logic Question paper with you

Question:The binary operation * is defined as follows

Which one of the following is equivalent to P∨Q?
(A) ¬Q * ¬P
(B) P * ¬Q
(C) ¬P * Q
(D) ¬P * ¬Q
Question:in order to add these two binary number 1111 + 1101. how many full and half adder ?
a)1 FA and 1 HA
b) 3 FA and 1 HA
c) 2 FA and 2 HA
d) 1 FA and 3 HA

Question:A master-slave flip-flop has the characteristic that
A) change in the input immediately reflected in the output
B) change in the output occurs when the state of the master is affected
C) change in the output occurs when the state of the slave is affected
D) both the master and the slave states are affected at the same time

The output of a logic circuit is a 1 only when any one of the following patterns is present at its three inputs:
000, 001, 010, 011, 110

A majority gate is a digital circuit whose output is a 1 if the majority of the inputs are a 1 otherwise the output is a 0. Design a logic circuit for a 3-input majority gate and a 5-input majority gate.

GATE Digital Logic Questions

July 24th, 2012 06:23 PM
Re: GATE Questions on Digital Logic

Here is some Digital Logic question papers:

1. On pages 226-227 of the textbook, questions: 3, 5, 8, 9, 11.
#3. Use a truth table to show that X = (X AND Y) OR (X AND NOT Y)
0 0 | 0
0 1 | 0
1 0 | 1
1 1 | 1
Notice that in the truth table, the value of (X AND Y) OR (X AND NOT Y) always has the value of X.

#5. Show and the AND function can be constructed from two NAND gates. Since (A AND B) is equivalent to (NOT (NOT (A AND B)), you can construct AND by

2. Build a decoder with three input lines but with only six output lines. If the value of the input corresponds to 6 or 7, then all output lines should be asserted to signal an error.

This is just like an ordinary 3-input, 8-output decoder, except that if the input1 and input2 are both 1 (resulting in an input value of 6 or 7), all the outputs should be 1. This is accomplished by ANDing input1 and input2 and then sending that result to be OR’d with the normal value for each output. See below.

Complete question paper is available in pdf file which have uploaded here. Feel free to download this question paper.
July 24th, 2012 03:07 PM
Bhagesh Mehra
GATE Questions on Digital Logic

I need GATE Questions on Digital Logic so I am looking for it in net since four hours but couldn’t get any site. Can you help me in this regard? Mention me sites providing questions and answers on Digital Logic Gates with explanation.

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