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Old May 27th, 2014, 10:40 AM
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Default IETE AMIETE-ET(Old Scheme) Analog & Digital Electronics previous years question paper

Can you please give me the IETE AMIETE-ET(Old Scheme) Analog & Digital Electronics previous years question papers?
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  #2  
Old May 27th, 2014, 03:07 PM
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Join Date: May 2011
Default Re: IETE AMIETE-ET(Old Scheme) Analog & Digital Electronics previous years question p

As you want to get the IETE AMIETE-ET(Old Scheme) Analog & Digital Electronics previous years question papers so here is the information of the same for you:

Some content of the file has been given here:

Q.1 Choose the correct or the best alternative in the following: (210)
a. If an inverting amplifier has the non inverting pin of the op-amp connected
to ground, the inverting pin of the op-amp will be _________.
(A) at ground (B) at virtual ground
(C) equal to in V (D) equal to out V
b. Slew rate distortion is more prevalent in circuit with _________.
(A) small input voltage swings (B) large input voltage swings
(C) small output voltage swings (D) large output voltage swings
c. The cut off frequency is also referred to as the ________.
(A) half power point (B) low end frequency
(C) higher end frequency (D) both (B) and (C)
d. The network of resistors containing only two values are known as
(A) binary divider (B) binary ladder
(C) analog divider (D) analog ladder
e. When a transistor switch is in saturation CE V is approximately equal to
________
(A)
CC V (B) B V
(C) 0.2V (D) 0.8V
f. Which of the following flipflop is used as latch?
(A) JK flipflop (B) SR flipflop
(C) D flipflop (D) T flipflop
g. TTL totempole output stage is primarily used to
(A) increase the noise margin of the gate
(B) decrease the output switching delay
(C) facilitate a wired OR logic connection
(D) increase the output impedance of the circuit
h. A full adder can be made of
(A) two half adder (B) two half adder and a NOR gate
(C) two half adder and OR gate (D) two half adder and AND gate
i. A ring counter consisting of 5 flipflop will have
(A) 5 states (B) 10 states
(C) 32 states (D) states
j. LEDs function like normal diodes except they have a forward voltage drop
of approximately __________
(A) 0.3 V (B) 0.7 V
(C) 1V (D) 2V
Answer any FIVE Questions out of EIGHT Questions.
Each question carries 16 marks.
Q.2 a. Find the Butterworth transfer function that meets the following low pass
filter specification KHz 10 fp , dB 1 Amax , dc gain = 1, dB 25 Amin . (8)
b. Explain “offset voltage” and “offset current” of an opamp also discuss the
technique for minimizing the same. (8)
Q.3 a. Explain the basic principle of switching capacitor filter and also explain
how a switching capacitor behave as a resistance. (6)
b. Draw the block diagram for a counting type A/D converter and explain the
operation for the system. (10)
Q.4 a. Explain the physical significance of storage time and transition time in
diode switching. (8)
b. Explain the terms
(i) Noise margin (ii) Propagation delay
(iii) Power dissipation (iv) fan in and fan out (8)
Q.5 a. Draw a totem pole output with a TTL gate & explain its operation. (10)
b. Generate the following combination logic equation using a 4 input
multiplexer A B C A B C A B C A B C Y (6)
AE09 / JUNE – 2011 3 AMIETE – ET (OLD SCHEME)
Q.6 a. Explain the system for a 4 bit odd parity checker. (8)
b. Show how a SR flipflop can be constructed using NOR gates and explain
the different states of the SR flipflop. (8)
Q.7 a. Explain the block diagram of a ROM and what hardware constitutes the
memory element. (8)
b. Draw the circuit diagram of a simple instrumentation amplifier. Also
derive the expression of output voltage in terms of the input value and
circuit resistance. (8)
Q.8 a. Sketch the architecture of an NMOS op-amp and list three reasons why this
architecture is employed. (8)
b. Explain how a PLA can be used to realize a logical expression. (8)
Q.9 Write short note on any TWO of the following: (82)
(i) BJT inverter
(ii) Dynamic MOS
(iii) Shift register
(iv) Programmable Array logic







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  #3  
Old January 15th, 2015, 01:11 PM
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Join Date: Nov 2011
Default Re: IETE AMIETE-ET(Old Scheme) Analog & Digital Electronics previous years question p

It’s not given on site it’s different from that paper.

As you want to get IETE AMIETE-ET (Old Scheme) Analog & Digital Electronics question paper so here I am giving you some questions of that paper:

Q.1 Choose the correct or the best alternative in the following: (2×10)
a. In a differential amplifier, CMRR can be improved by using an increased
(A) emitter resistance (B) collector resistance
(C) source resistance (D) power supply voltage
b. Ability of an operational amplifier to provide sufficient differential mode
signal but to reject the common mode signal is given by
(A) Closed loop gain
(B) Open loop gain
(C) CMRR.
(D) none of the above.
c. A notch filter is a
(A) Wide band pass filter. (B) Narrow band pass filter.
(C) Wide band reject filter. (D) Narrow band reject filter
d. The number of comparators required to build an eight-bit simultaneous or
flash A/D converter is
(A) 127 (B) 63
(C) 255 (D) 8
e. A data selector is also called a
(A) De-multiplexer (B) Priority encoder
(C) Multiplexer (D) Decoder
f. In a 1:16 demultiplexer, the number of control inputs will be
(A) 4 (B) 1
(C) 2 (D) 16
g. Identify the slowest of the family listed below
(A) LSTTL (B) TTL
(C) ECL (D) Low Power TTL
h. The number of flip-flops needed to construct a BCD decade counter is
(A) 4 (B) 3
(C) 10 (D) none of these
i. Size of ROM required to implement a 16:1 multiplexer would be
(A) 512k*2 (B) 1M*1
(C) 1M*2 (D) 128*6
j. A dynamic RAM consist of
(A) 6 transistors. (B) 2 transistors and 2 capacitors
(C) 1 transistors and 1 capacitors. (D) 2 capacitors only

IETE AMIETE-ET(Old Scheme) Analog & Digital Electronics Question Paper



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