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Here I am sharing the previous year Question paper of JNTU for B.Tech in Electronics and Instrumentation Engineering-Digital IC Applications Exam 1. (a) What are the parameters that are necessary to define the electrical charac- teristics of CMOS circuits? Mention the typical values of a CMOS NAND gate. (b) Design a CMOS 4-input AND-OR-INVERT gate. Draw the logic diagram and function table. 2. (a) Mention the DC noise margin levels of ECL 10K family. (b) A single pull-up resistor to +5V is used to provide a constant-1 logic source to 15 different 74LS00 inputs. What is the maximum value of this resistor? How much high state DC noise margin can be provided in this case? [6+10] 3. (a) Write a VHDL Entity and Architecture for a 3-bit synchronous counter using Flip-Flops. (b) Explain the use of Packages. Give the syntax and structure of a package in VHDL. 4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural VHDL program for the same. 5. Design a 10 to 4 encoder with inputs 1- out of ?10 code and outputs in BCD? Provide the data flow style VHDL program? 6. Write VHDL program for 1-bit comparator circuit with the input bits and equal, grater than and less than inputs from the previous stage and the outputs contain equal, greater than and less than conditions. Using this entity write VHDL program for 16-bit comparator using data flow style. Do not use any additional logic for this purpose. 7. (a) Differentiate between ripple counter and synchronous counter? Design a 4-bit counter in both modes and estimate the propagation delay ![]() Address: Jawaharlal Nehru Technological University Main Road, Kukatpally Housing Board Colony, Kukatpally,Hyderabad, Andhra Pradesh, 500085 040 2315 8661 Map:
__________________ Answered By StudyChaCha Member Last edited by Aakashd; August 4th, 2018 at 06:29 PM. |
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Here I am providing the list of few questions of JNTU B.Tech in Electronics and Instrumentation Engineering-Digital IC Applications exam question paper which you are looking for . 1. (a) Design CMOS transistor circuit for 3-input AND gate. With the help of function table explain the operation of the circuit diagram. (b) Design a CMOS transistor circuit that has the functional behavior as f(x) = (a + b) (b + c)(a + c) Also draw the relevant circuit diagrams. [8+8] 2. (a) Design a transistor circuit of 2-input ECL NOR gate. Explain the operation with the help of function table. (b) A single pull-up resistor to +5V is used to provide a constant-1 logic source to 15 different 74LS00 inputs. What is the maximum value of this resistor? How much high state DC noise margin can be provided in this case? [8+8] 3. (a) Explain the various data types supported by VHDL. Give the necessary ex- amples. (b) Discuss the case statement and its use in the VHDL program. [8+8] 4. Design a logic circuit to detect prime number of a 5-bit input. Write the structural VHDL program for the same. JNTU B.Tech in Electronics and Instrumentation Engineering-Digital IC Applications exam question paper ![]()
__________________ Answered By StudyChaCha Member Last edited by Aakashd; August 4th, 2018 at 06:29 PM. |