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Will you please share the previous year question paper of Pune University for SE Information Technology - Digital Electronics & Logic Design Exam?? Here I am sharing the previous year question paper of Pune University for SE Information Technology - Digital Electronics & Logic Design Exam Convert the following hexadecimal numbers into their equivalent octal numbers and binary numbers. (1) A72E (2) BD6.7 (3) 0.AF54 (4) DF (5) FF [10] Q a) Explain the standard TTL characteristics in detail [8] b) Draw and explain the working of 2-input CMOS NOR gate. [8] OR Q a) Why is it necessary to interface between TTL and CMOS? Draw and explain the circuit arrangement of interfacing CMOS gate to number of TTL gates. b) Explain with the help of circuit diagram 2-input TTL NAND gate with Totem Pole output driver [8] Q. a) Design and implement BCD to Excess-3 code converter using dual 4:1 multiplexers and some logic gates. [8] b) Design 8-bit comparator using IC-7485 [8] OR Q a) Design and implement BCD to Excess-3 code converter using required logic gates. Show truth table K-maps and circuit diagram of your design [8] b) Draw and explain 4-bit BCD subtractor using IC 7483. Explain the operation on BCD numbers: 5-7. ![]() ![]() ![]() ![]() ![]() ![]() ![]() ![]() Rest of the Questions are attached in below file which is free of cost Address: University Of Pune Ganeshkhind, Pune, Maharashtra 411007 020 2560 1099 Map: Last edited by Aakashd; June 28th, 2019 at 02:31 PM. |
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Here I am providing the list of few questions of Pune University SE Information Technology Digital Electronics & Logic Design exam question paper which you are looking for . 1. (a) Do the required conversions for the following numbers : [6] (i) (BF8)16 = (_____)10 (ii) (1000)10 = (_____)8 (iii) (377)8 = (_____)16. (b) What are different ways of representing signed binary numbers ? Explain with examples. [6] (c) Solve the following equation using K map minimization technique. Draw the diagram for the output : [6] Z = f(A, B, C, D) = M(0, 1, 6, 7, 8, 9). Or 2. (a) Perform the following operations : [8] (i) (FFFF)16 – (10000)10 = (_____)10 (ii) (765)8 + (365)8 = (_____)16 (iii) (658)16 + (975)16 = (_____)16 (iv) (1011.101)2 = (_____)10. (b) Solve the following equation using corresponding minimization technique. Draw the diagram for the output : [6] Z = f(A, B, C, D) = m(2, 4, 6, 11, 12, 14) + d(3, 10). (c) What are the advantages of Quine McClusky minimization technique over K map ? [4] 3. (a) Define the following terms related to logic families. Mention typical values for standard TTL family : [8] (i) Propagation delay (ii) Fan-out (iii) VIL, VIH (iv) Noise margin. (b) Draw the structure of two input CMOS NAND gate. Explain its working. [4] (c) List differences between CMOS and TTL. [4] Pune University SE Information Technology Digital Electronics & Logic Design exam question paper ![]() ![]() ![]() ![]() ![]()
__________________ Answered By StudyChaCha Member Last edited by Aakashd; August 6th, 2018 at 11:38 AM. |
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