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Mumbai university BE CS 3rd Sem digital logic design and Application exam Paper Here I am giving you question paper for Mumbai university be in computer science 3rd sem digital logic design and application examination in PDF file attached with it .. 1. (a) Convert (47.3)7 TO B~D I Excess- 3 I and1,GrayCode. (b) Perform the following operation using 2' s complement method (Ii) (246) 7 -(435 )10 i (45) 10 * (23 ) 10 @ Perform the followingoperation with out converting into any other base. (d) Explain in brief combinational PLD'S. (e) State Distribution Laws for simplification of Boolean equation and prove it. 2. (a) Obtain HammingCode for the data (1101).Why HammingCode is called as Error Detecting Code (4) (b ) GivenLogicEquation ~ F = AB+ AC+ C+ AD+ ABC+ A~C Design K- Map for the given Equation. (4) ." Express in SOP Eq~ation. (4) (iii) Minimise and Realise the above equation using NOR gates only. (4) (iv)Realise the above equation in Standard pas and using NAND gates only. (4) 3.(a) Minimise the following equation using NOR gates only. (5) I F(W,X,Y.Z) = n M (1.2.3.8.9.1O.f1.14) * d( 7,15) (b) Provethe follwingequation using BooleanLaws. (5) (i) (B+A ) ( C+D) (A+ C) ( B+D) =BC+AD (II) (A.B. A) (A B B) = A8B @ what is a carry look ahead adder. design 4 bit carry look ahead adder using gates. (5) (d)A Car manufacturing Company wants to design a logiccct. to allow the car to start only in the following condition (5) only when driver and front seat co- passenger are sitting with their seat belt on. if no passenger is sitting and only the driver is sitting with the seat belt on. .4.(a) (i) Implementthe following expression using only one 8 : I Mux. and few gates. (5) F =~m (0,1,3,4,5,7,9,10,1£,13,15) I (ii) ImplementthefollowingexpresJionusingonlyone4 : 1Mux.andfewgates. (5) F=~m (0,1,2,3,6, 7,9,10,13;15) (b) Using the Quine Mc Cluskey Method minimization technique simplify F = ~m ( 1,2,6,8,10,11,14,15) + d (5,9) Mumbai university BE CS 3rd Sem digital logic design and Application exam Paper Mumbai university BE CS 3rd Sem digital logic design and Application exam Paper Last edited by Aakashd; March 8th, 2020 at 02:26 PM. |
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Re: Mumbai university BE CS 3rd Sem digital logic design and Application exam Paper
As per your request here I am sharing a Mumbai university BE CS 3rd Sem digital logic design and Application exam Paper The syllabus contains the following: Boolean algebra Analysis and design of combinational logic Sequential logic Programmable logic devices CAD tools Total mark of the paper is 100. Mumbai university BE CS 3rd Sem digital logic design and Application exam Paper
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