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  #1  
Old April 27th, 2014, 12:19 PM
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Default Sathyabama University BE Electronics & Instrumentation Engineering III Sem Digital Lo

Can any one here provide me the previous year question paper of Sathyabama University of BE Electronics & Instrumentation Engineering III Sem Digital Logic Theory and Design Exam??
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  #2  
Old April 27th, 2014, 01:59 PM
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Default Re: Sathyabama University BE Electronics & Instrumentation Engineering III Sem Digita

As per your request here I am sharing the previous year question paper of Sathyabama University of BE Electronics & Instrumentation Engineering III Sem Digital Logic Theory and Design Exam

PART - A (10 x 2 = 20)
Answer ALL the Questions
1. Given the two binary numbers X = 1010100 and Y = 1000011,
perform the subtraction (a) X – Y and (b) Y – X using 2’s
complements.
2. State De Morgan’s theorem.
3. Compare CMOS and NMOS.
4. What are tri-state gates?
5. Give the comparison between combinational circuits and
sequential circuits.
6. Difference between PROM, PLA, PAL.
7. What is race around condition?
8. Explain the procedure for state minimization.
9. Define race.
10. What are essential hazards?

PART – B (5 x 12 = 60)
Answer All the Questions

11. Simplify the Boolean function
F (A,B,C,D,E) = (0,1,4,5,16,17,21,25,29)
(or)

12. Express the following function in sum of minterms and product
of maxterm F(A,B,C,D) = B’D + A’D + BD

13. Explain TTL logic gate with a neat diagram.
(or)

14. Explain NMOS and CMOS logic gates with a neat diagram.

15. Design a combinational circuits which converts BCD to Excess-3
Code.
(or)

16. With a neat circuit diagram explain PAL.

17. A clocked sequential circuit has three states A,B,C and one input
X. As long as the input X is 0, the circuit alternates between the
states A and B. If the input X becomes 1 (either in state A or in
State B), the circuit state C and remains in state C as long as X
continues to be 1. The circuits returns to state A, if the input
becomes 0 once again and from then on repeats its behaviour.
Assume that the state assignments are A = 00, B = 01 and C = 10.
(a) Draw the state diagram of the circuit (b) Give the state table
for the circuit. (c) Draw the circuit using D-Flip-Flops.
(or)

18. Explain Synchronous Counters with neat diagram.

19. Explain Race free assignment using an example.
(or)

20. Explain pulse mode sequential circuits.

Address:
Sathayabama University
Jeppiaar Nagar, Rajiv Gandhi Road, Chennai,
Chennai, Tamil Nadu 600 119 ‎
044 2450 3150

Map:

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  #3  
Old January 17th, 2015, 10:57 AM
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Join Date: Apr 2013
Default Re: Sathyabama University BE Electronics & Instrumentation Engineering III Sem Digita

Here I am providing the list of few questions of Sathyabama University B.E in Electronics and Instrumentation Engineering-3rd Sem Digital Logic Theory and Design Paper which you are looking for .
(Sathyabama University B.E in Electronics and Instrumentation Engineering-3rd Sem Digital Logic Theory and Design Papers)

PART – A (10 x 2 = 20)
Answer All the Questions
1. Convert the following binary number to octal and hexadecimal
111101000.0111.
2. What is Karnaugh map?
3. List five series of TTL circuits
4. In what type of application should ECL not be used?
5. Define the term glitch.
6. Define the term strobing.
7. What do you mean by zero suppression?
8. What is a carry?
9. What is the race condition?
10. Give an example for sequential circuit.
PART – B (5 x 12 = 60)
Answer All the Questions
11. Perform the following conversions:
(a) 43510 to octal
(b) 5408 to binary
(c) 41216 to binary
Also perform binary multiplication of
(i) 1001 x 110
(ii) 111 x 101
(or)
12. Design a digital system that adds and subtracts two binary fixed
point numbers in sign 2’s complement form.
13. (a) Describe the major difference between a bipolar integrated
circuit and an MOS integrated circuit. (7)
(b) What are the advantages of ECL over other IC
technologies? (5)
(or)
14. (a) Does CMOS or TTL perform better in a high-noise
environment? Why? (7)
(b) Explain why an open TTL input acts as a HIGH. (5)
15. (a) Implements a full adder circuit with a decoder and two OR
gates. (8)
(b) Explain how a PLA differs from a ROM. (4)
(or)
16. Explain the working of following circuits:
(a) MUX
(b) DEMUX
(c) Encoder/ Decoder.
17. Design a counter using T flip-flop for binary counting sequence:
0, 1, 3, 7, 6, 4 and repeat.
(or)
18. Design BCD to decimal decoder.
19. (a) Write down the output specifications of sequential circuit.(8)
(b) Describe about stable and unstable states of sequential
circuit. (4)
(or)
20. Write short notes on:
(a) Application of sequential circuits
(b) Race free assignment.
(c) Hazards.
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