CUSAT Hardware Modelling Question Paper - 2017-2018 StudyChaCha

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Old August 21st, 2017, 12:30 PM
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Default CUSAT Hardware Modelling Question Paper

Hi I am interested in having the syllabus for the Hardware Modelling Elective course in VI Semester of the B. Tech in ECE branch at CUSAT as well as the question paper for the special supplementary examination held by the University?
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Old August 21st, 2017, 12:52 PM
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Default Re: CUSAT Hardware Modelling Question Paper

The syllabus for the Hardware Modelling Elective course in VI Semester of the B. Tech in ECE branch at CUSAT as well as the question paper for the special supplementary examination held by the University is provided below:

Hardware Modelling Syllabus


Module I
Introduction: Hardware Abstraction- Basic Terminology- Entity Declaration- Architecture Body- Basic Language
Elements –Identifiers- Data Objects- Data Types- Operators. Example designs: Basic Combinational Circuits.
Behavioural Modelling: Process Statement- Variable Assignment Statement- Signal Assignment Statement- Wait
Statement- If Statement - Case Statement- Null Statement- Loop Statement- Exit Statement- Next StatementAssertion
Statement- Report Statement- Other Sequential Statements- Multiple Processes

Module II
Dataflow Modelling: Concurrent Signal Assignment Statement- Concurrent versus Sequential Signal AssignmentMultiple
Drivers- Conditional Signal Assignment Statement- Modelling of Basic Binary Arithmetic Circuits,
Sequential Circuits, Registers.
Structural Modelling: Component Declaration- Component Instantiation- Resolving Signal Values - GenericsConfigurations

Module III
Subprograms- Subprogram Overloading- Operator Overloading- Signatures- Packages and Libraries. Models of
RAM.
Advanced Features: Generate Statements- Aliases- Attributes.
Model Simulation: Simulation- Writing a Test Bench- Reading Vectors from a Text File.
Modelling Delays- State Machine Modelling.
Module IV
CPLDs and FPGA: FPGA types- FPGA versus custom VLSI- FPGA based system design
FPGA programming technologies: antifuse-static RAM-EPROM-EEPROM.
FPGA families: Actel- Actel1 logic module, Xilinx- xilinx LCAXC3000CLB, Altera-Altera FLEX logic element.
Logic expander.

References:

1. S S Limaye,VHDL – A Design Oriented Approach,TMH,2008,ISBN: 13: 978-0-07-064825-8, ISBN: 10:
0-07-064825-5

2. Micheal John Sebastian Smith, Application Specific Integrated Circuits,Pearson,2001,ISBN: 978-81-
7758-408-0

3. Gaganpreet Kaur, VHDL basics to programming, Pearson,2011

4. Stephen Brown,Zvonko Vranesic ,Fundamentals of Digital Logic Design with VHDL,TMH,2/e,2007

5. Cyril, Fundamentals of HDL Design,Pearson,2009,ISBN: 978-81-317-3247-2

6. Mark Zwolonski,Digital System Design with VHDL,Pearson,2/e,2004

7. Zainalabedin Navabi, VHDL Modular Design and Synthesis of Cores and Systems, TMH,3/e,2008

8. Douglas L. Perry, VHDL Programming by Example,TMH,4/e,2002

9. John F Wakerly, Digital Design Principles and Practices,Pearson,4/e,2008
Special Supplementary Examination Question Paper for the Hardware Modelling Elective course in VI Semester of the B. Tech in ECE branch held by the CUSAT

Special Supplementary Examination Question Paper for the Hardware Modelling Elective course in VI Semester of the B. Tech in ECE branch held by the CUSAT


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