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  #1  
Old July 25th, 2012, 02:56 PM
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Default JNTU Kakinada 4-1 Online Bits 2nd Mid

Hy Dear here I am searching for the Jawaharlal Nehru Technological University Kakinada 4-1 Online Bits 2nd mid so please can you give me the information about this topic and also provide me the page where I can get the details of this topic?
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Old July 25th, 2012, 04:49 PM
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I am giving you the 2nd Mid JNTU online examination paper for ECA. You can well, prepare for the examinations with the question paper. I am sharing the information from the official website for your reference.

I am sharing the pdf file containing the question paper of JNTU online examination paper for2nd Mid ECA. Feel free to use it.
Attached Files
File Type: pdf JNTU Mid 2 question for ECA.pdf (1.01 MB, 27 views)
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Old October 12th, 2012, 07:26 PM
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for what u have give and what showing as result
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Old October 13th, 2012, 10:11 PM
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Hy Dear here I am searching for the Jawaharlal Nehru Technological University Kakinada 4-1 Online Bits 2nd mid so please can you give me the information about this topic and also provide me the page where I can get the details of this topic?
jntuworld lo 2nd mid bits yesterday post you can seeeeeeeeee
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Old October 13th, 2012, 10:16 PM
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give me your mail i will send it
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Old October 14th, 2012, 07:22 PM
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Default Re: JNTU Kakinada 4-1 Online Bits 2nd Mid

WHERE NP 4-1 2ND MID ONLINE BITS
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Old April 25th, 2013, 06:23 PM
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Default JNTU KAKINADA 4-1 ONLINE BITS 2ND MID

Can you provide me JNTU KAKINADA 4-1 ONLINE BITS 2ND MID papers?
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  #8  
Old April 26th, 2013, 02:44 PM
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As you are looking for JNTU KAKINADA 4-1 ONLINE BITS 2ND MID papers here I am providing some questions related to it


1. Assume we have a computer where the clock per
instruction (cpi) is 1.0 when all memory accesses hit in the
cache. The only data accesses are loads and stores and these
total 50 % of the instructions. If the miss penalty is 25 clock
cycle and miss rate is 2 %,how much faster would the
computer be if all the instructions were cache hits.
a. 0.25
b. 0.75
c. 1.5
2. Which among the following is not a cache optimization
technique
a. Reducing the miss penalty
b. reducing the miss rate
c. reducing the miss penalty or miss rate via serialism
d. reducing the time to hit in cache
3. Average memory access time= _ _ _ _ _ _ _ _ _
a. hit time+miss rate*miss penalty
b. miss rate + hit time*miss penalty
c. miss penalty + hit rate * miss rate
d. hit time+hit rate*miss penalty
4. Memory stall cycles= _ _ _ _ _ _ _ _ _ _
a. number of hits*miss penalty
b. number. of misses* miss penalty
c. Number of hits * hit time
d. number of misses * hit time.
5. If the memory hierarchies of the two computers are
identical, the cpu with _ _ _ _ _ _ _ _clock rate has a _ _ _ _
_ _ _ _ _ number of clock cycles per miss.
a. higher, smaller
b. higher, larger
c. lower, smaller
d. lower, larger
6. Cache memory works on the _ _ _ _ _ _ _
a. Principle of locality
b. working set
c. global memory
d. thumb rule.
7. when the cpu finds a requested data item in cache, it is
called a _ _ _ _ _ _ _
a. cache miss
b. cache hit
c. memory miss
d. memory hit
8. The _ _ _ _ _ _ _ the CPI execution, the _ _ _ _ _ _ _ the
relative impact of the fixed no of cache miss clock cycles.
a. lower,lower
b. higher,lower
c. lower, higher
d. higher, higher


for the rest of papers here I am providing PDF file
ONLINE BITS 2ND MIDs


ONLINE BITS 2ND MID
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File Type: pdf ONLINE BITS 2ND MID.pdf (272.0 KB, 5 views)
File Type: pdf ONLINE BITS 2ND MIDs.pdf (622.7 KB, 3 views)
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Old November 28th, 2013, 10:16 PM
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give me your mail i will send it
nareshboaz@gmail.com.
bio medical engineering(bme)
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Old February 18th, 2014, 02:43 PM
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Can any one here provide me the Jawaharlal Nehru Technological University (JNTU), Kakinada 4-1 Online Bits 2nd Mid Question paper of Advanced Computer Architecture (ACA)???
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Old February 18th, 2014, 03:05 PM
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Jawaharlal Nehru Technological University, Kakinada (JNTUK) is a state university and was established on 16 July 1946 as the College of Engineering, Vizagapatnam

Jawaharlal Nehru Technological University (JNTU), Kakinada Conduct Mid Online Exam.

Here I am sharing the JNTU Kakinada 4-1 Online Bits 2nd Mid Question paper of Advanced Computer Architecture (ACA) with you

_ _ _ _ _ _ _ _ _ _ is the no of misses in cache divided by the total no of memory
accesses to this cache
a.local miss rate
b.global miss rate
c.local miss penalty
d.global miss penalty

Which miss penalty technique is based on the observation that the cpu normally
needs just one word of the block at a time
a.multilevel caches
b.critical word first and early restart
c.giving priority to read misses over writes
d.merging write buffers

Write buffers hold the update value of a location needed on a _ _ _ _ _ _ _ _
write miss
read miss
write hit
read hit

_ _ _ _ caches rely of write buffers
write back
write through
optimized
victim


1. Assume we have a computer where the clock per instruction (cpi) is 1.0 when all
memory accesses hit in the cache. The only data accesses are loads and stores
and these total 50 % of the instructions. If the miss penalty is 25 clock cycle and
miss rate is 2 %,how much faster would the computer be if all the instructions
were cache hits.
a.
b.
c.
d.
2. Which
0.25
0.75
1.5
1.75
among the following is not a cache optimization technique
a.Reducing the miss penalty
b.reducing the miss rate
c.reducing the miss penalty or miss rate via serialism
d.reducing the time to hit in cache
3. Average memory access time= _ _ _ _ _ _ _ _ _
a.hit time+miss rate*miss penalty
b.miss rate + hit time*miss penalty
c.miss penalty + hit rate * miss rate
d.hit time+hit rate*miss penalty
4. Memory stall cycles= _ _ _ _ _ _ _ _ _ _
a.number of hits*miss penalty
b.number. of misses* miss penalty
c.Number of hits * hit time
d.number of misses * hit time.
5. If the memory hierarchies of the two computers are identical, the cpu with _ _ _ _
_ _ _ _ clock rate has a _ _ _ _ _ _ _ _ _ number of clock cycles per miss.

6. Cache
higher, smaller
higher, larger
lower, smaller
lower, larger
memory works on the _ _ _ _ _ _ _
a.Principle of locality
b.working set
c.global memory
d.thumb rule.
7. when the cpu finds a requested data item in cache, it is called a _ _ _ _ _ _ _
a.cache miss
b.cache hit
c.memory miss
d.memory hit
8. The _ _ _ _ _ _ _ the CPI execution, the _ _ _ _ _ _ _ the relative impact of the
fixed no of cache miss clock cycles.
a.lower,lower
b.higher,lower
c.lower, higher
d.higher, higher
9. CPU time = _ _ _ _ _ _ _ _

10. Miss
cpu execution clock cycles *(memory stall clock cycles+clock cycle time)
cpu execution clock cycles +memory stall clock cycles+clock cycle time
(cpu execution clock cycles +memory stall clock cycles)*clock cycle time
cpu execution clock cycles+ memory stall clock cycles*clock cycle time
penalty is measured in _ _ _ _ _ _ _ _

a.cpu clock cycles for a hit
b.cpu clock cycles for a miss
c.cpu clock cycles to execute an instruction
d.cpu clock cycles to access cache.
11. What are the local and global miss rates of second level cache if in 1000 memory
references there are 40 misses in the first level cache and 20 misses in the
second level cache
a.50 % and 20 %
b.2 % and 50 %
c.50 % and 2 %
d.20 % and 50 %
12. Depending on the program, a _ _ _ _ _ _ _ _ victim cache might remove one- quarter of the misses in a 4KB direct mapped data cache
a.one entry
b.two entry
c.four entry
d.five entry
13. _ _ _ _ _ _ _ _ _ _ is the no of misses in cache divided by the total no of memory
accesses to this cache
a.local miss rate
b.global miss rate
c.local miss penalty
d.global miss penalty
14. Which miss penalty technique is based on the observation that the cpu normally
needs just one word of the block at a time
a.multilevel caches
b.critical word first and early restart
c.giving priority to read misses over writes
d.merging write buffers
15. _ _ _ _ _ _ _ _ cache contains only blocks that are discarded from a cache
because of a miss
a.write back
b.write through
c.optimized
d.victim
16. Which miss penalty reduction technique ignores the cpu, concentrating on the
interface between the cache and main memory

17. What
multilevel caches
critical word first and early restart
giving priority to read misses over writes
merging write buffers
is the miss penalty of L1 cache
a.hit time L2 + miss rate L1 * miss penalty L2
b.hit time L2 + miss rate L2 *miss penalty L2
c.hit time L1 + miss rate L2 *miss penalty L2
d.hit time L1+ miss rate L1 *miss penalty L2
18. Write buffers hold the update value of a location needed on a _ _ _ _ _ _ _ _

19. _ _ _

write miss
read miss
write hit
read hit
_ _ _ _ caches rely of write buffers
write back
write through
optimized
victim


21. _ _ _
victim caches
merging write buffer
multi level caches
critical word first and early restart
_ _ _ _ _ _ optimization reduces misses by improved temporal locality
a.loop interchange
b.blocking
c.pseudo associative cache
d.prediction
22. Which of the following statements is not true about blocking
a.reduces misses via improved temporal locality
b.it can also be used to help register allocation
c.blocking algorithms operate on entire rows or columns of an array
d.it exploits a combination of spatial and temporal locality
23. The latency of the 21264 data cache is _ _ _ _ _ _ clock cycles
a.1
b.2
c.3
d.4
24. _ _ _ _ _ _ _ _ optimization improves cache performance without affecting the
number of instructions executed
a.loop interchange
b.blocking
c.pseudo associative cache
d.prediction
25. Which miss rate reduction technique reduces miss rates without any hardware
changes
a.compiler optimizations
b.way prediction and pseudo associative caches
c.large caches
d.higher associativity
26. The very first access to a block cannot be in the cache, so the block must the
brought into the cache. These are called _ _ _ _ _ misses
a.

27. _ _ _
four- a.
b.
c.
d.
28. _ _ _
collision
conflict
capacity
compulsory
_ _ _ _ conflict misses -are due to going from eight way associative to
way associative
Eight way
four way
two way
one way
_ _ _ _ _ misses decreases as associativity increases
a.collision
b.capacity
c.compulsory
d.first reference
29. Which miss rate reduction technique is popular in off chip caches


large block size
larger caches
higher associativity
compiler optimizatio

30. If the upper level memory is smaller than what is needed for a program and a
significant percentage of the time is spend moving data between two levels in
the hierarchy, the memory hierarchy is said to _ _ _ _ _ _ _ _
a.crash
b.trash
c.fault
d.miss
31. What is the size of the page table, given a 32 bit virtual address, 4 KB pages and
4 bytes per page table entry
a.2MB
b.4MB
c.8MB
d.16MB
32. consider a logical address space of eight pages of 1024 words each, mapped on
to a physical memory of 32 frames . How many bits are there in the physical
address
a.10
b.13
c.15
d.18
33. Virtual memory system include a _ _ _ _ _ _ _ _ bit, since the cost of an
unnecessary access to the next lower level is so high
a.valid
b.invalid
c.dirty
d.modify
34. The size of the page table is _ _ _ _ _ _ _ the page size
a.directly proportional to
b.inversely proportional to
c.does not depend on
d.equal to
35. Transferring _ _ _ _ _ _ _ _ _ pages to or from secondary storage, possibly over
a network, is more efficient than transferring _ _ _ _ _ _ _ _ pages
a.larger, larger
b.larger, smaller
c.smaller , larger
d.smaller, smaller
36. _ _ _ _ _ _ _ _ memory, divided physical memory into blocks and allocates them
to different processes
a.primary
b.cache
c.magnetic bubble
d.virtual
37. Which mechanism allows the same program to run in any location in physical
memory
a.
b.
c.
d.
38. With
reloading
Relocation
memory mapping
linking
virtual memory, the cpu produces _ _ _ _ _ _ _ _ addresses
a.virtual
b.physical
c.relocatable
d.linkage
39. To reduce the address translation time , computers use a cache dedicated to
these address translations called a _ _ _ _ _ _ _ _ _

a.
b.
c.
d.
40. _ _ _
TLB
paging buffer
segmented buffer
inverted page table
_ _ _ _ occurs in paging
a.internal fragmentation
b.external fragmentation
c.variable size partition
d.memory interleaving
41. The civilian programs are the _ _ _ _ _ _ trusted and hence, have the _ _ _ _ _ _
limited range of accesses
a.most , most
b.least , least
c.most , least
d.least , most
42. A descriptor pointing to a _ _ _ _ _ _ _ _ segment is placed in the global
descriptor table, while a descriptor for a _ _ _ _ _ _ _ _ _ _ segment is placed in
the local descriptor table.
a.shared, private
b.private, shared
c.shared, public
d.public, shared.
43. _ _ _ _ _ _ _ added to the cpu protection structure expand memory access
protection from two levels to many more
a.rings
b.bounds
c.uses
d.locks
44. In alpha memory management, which protection field allows the kernel to read
the data within the page
a.valid
b.user read enable
c.kernel read enable
d.kernel write enable
45. Alpha 21264 employs _ _ _ _ _ _ _ _ TLBs to reduce address translation time
a.1
b.2
c.3
d.4
46. In _ _ _ _ _ _ _ , the cpu and the memory is shared among several interactive
uses at the same time, giving the illusion that all users have their own
computers
a.multiprogramming
b.timesharing
c.multiprocessors
d.real time systems
47. In alpha memory management, _ _ _ _ _ _ _ _ _ is reserved for the operating
system kernel, has uniform protection for the whole space, and does not use
memory management
a.seg 0
b.kseg
c.seg 1
d.seg 2.
48. The alpha memory management uses a _ _ _ _ _ _ _ page table to map the
address space to keep the size reasonable
a. inverted
b.TLB
c.two level hierarchical
d.three level hierarchical
49. Segment registers in the IA - 32 contains and index to a virtual memory data
structure called a _ _ _ _ _ _ _ table
a.
b.
c.
d.
50. _ _ _
tions
a.
b.
c.
d.
51. what
up of
page
segment
mapping
descriptor
_ _ _ _ field in the segment descriptor of IA-32 specifies the valid opera
and protection levels for operations that use this segment
limit
attributes
access bit
base
fraction of the original computation can be sequential to achieve a speed
80 with 100 processors?
a.0.25
b.0.5
c.0.75
d.1
52. What is the remote request cost for an application running on a 32- processor
Multiprocessors, which has a 400ns time to handle reference to a remote
memory. The processors clock rate is 1GHz
a.400 cycles
b.200 cycles
c.100 cycles
d.800 cycles
53. Which of the following is a false statement regarding distributed shared memory
multiprocessors.
a.they are also called NUMA's
b.communication occurs through a shared memory
c.It is a cost - effective way to scale the memory bandwidth
d.It increases the latency for accesses to the local memory
54. A multi computer consisting of completely separate computers connected on a
local area network are called _ _ _ _ _ _ _ _
a.
b.
c.
d.
55. What
Nodes
Workstations
Server
Cluster
is the interconnection network used in cray T3E multiprocessors?
a.multiple buses
b.farshypercube
c.2-way 3D torus
d.8 X 8 Cross bar
56. Vector architectures are the largest class of processors of _ _ _ _ _ _ type
a.SISD
b.SIMD
c.MISD
d.MIMD.
57. In which of the multiprocessors communication of data is done by explicitly
passing messages among the processors?
a.
b.
c.
d.
message passing multiprocessors
distributive shared memory multiprocessors
Symmetric shared memory multiprocessors
asymmetric multiprocessors
58. Which is the probable architecture for on-chip multiprocessors
a.
b.
c.
d.
59. What
a.
b.
c.
d.
60. What
MPP
SMP
moderate scale
shared virtual memory processors
is the maximum number of processes in sun star fire servers ?
2048
512
64
32
is the typical remote memory access time of HPV series?
a.500
b.300
c.1000
d.400
61. Which of the following statement is false regarding write-back cache
a.It harder to find the recent value of a data item
b.they use the same snooping scheme both for cache misses and for writes
c.they generate lower requirements for memory bandwidth
d.they are not preferable in multiprocessors.
62. An attempt to write a block in the _ _ _ _ _ _ _ state always generates a miss,
even if the block is present in the cache , since the block must be made _ _ _ _ _
_______
a.shared , Invalid
b.shared ,exclusive
c.Invalid , exclusive
d.exclusive, shared
63. Replication _ _ _ _ _ _ _ _ latency of access and _ _ _ _ _ _ _ _ contention for a
read shared data item
a.reduces ,increases
b.reduces , reduces
c.increases ,reduces
d.increases, increases
64. Write - back caches generate _ _ _ _ _ _ requirements for memory bandwidth ,
and slightly _ _ _ _ _ _ _ _ _ _ _ _ in complexity
a.lower, decrease
b.greater, decrease
c.lower, increase
d.greater, increase
65. If an operation is done with out intervening operation then the operation are _ _
________
a.deadlocked
b.starved
c.atomic
d.non atomic
66. The behavior of reads and writes to the same memory location is defined as _ _
_
a.coherence
b.consistency
c.dependency
d.serialization
67. Multiple writes to the same word with no intervening reads require _ _ _ _ _ _ _
write broadcast in an update protocol
a.
b.
Only one
One or two
c.atmost one
d.multiple
68. The processors with the sole copy of a cache block is normally called the _ _ _ _
of the cache block.
a.owner
b.user
c.dictator
d.master
69. If the CPU uses a multi level cache with the _ _ _ _ _ property , then every entry
in the Primary cache is required to be in the secondary cache
a.
b.
c.
d.
70. _ _ _
exclusion
inclusion
diffusion
shared
_ _ _ _ actions introduce the possibility that the protocol can deadlock
a.atomic
b.non atomic
c.illegal
d.sharing
71. Directory requests need to _ _ _ _ _ _ _ _ _ the set shares and also _ _ _ _ _ _ _
the set to perform invalidations
a.update , update
b.update,read
c.read , update
d.update,update
72. Optimization in directory protocols often add complexity by _ _ _ _ _ _ _ _ _
possibility of deadlock and by _ _ _ _ _ _ _ _ _ the types of messages that must
be handled.
a.increasing ,decreasing
b.increasing ,increasing
c.decreasing ,increasing
d.decreasing,decreasing
73. What message type and contents are to be transmitted from the local cache to
the home director when a processor P has a read miss at address A request data
and make P a read sharer
a.read miss A
b.Read miss P,A
c.Write miss A
d.Write miss P,A
74. _ _ _ _ _ _ _ are used to send a value from the home node back to the
requesting node
a.Invaliddate
b.Fetch
c.Data value reply
d.Data write back
75. Which directory request sets the shares to the identity of the new owner and the
state of the block remains exclusive.
a.Read miss
b.Data write back
c.write miss
d.Fetch
76. cache coherence is an accepted requirement in _ _ _ _ _ multiprocessors
a.
b.
c.
d.
small-scale
medium-scale
large-scale
very large scale
77. _ _ _ _ _ _ _ _ keeps the state of every block that may be cached
a.Record
b.File
c.Directory
d.Database
78. In which state exactly one processor has a copy of the cache block and it has
written the block , so the memory copy is out of date
a.shared
b.uncached
c.Invalid
d.exclusive
79. _ _ _ _ _ _ _ _ _ _ is the node where the memory location and the directory
entry of an address reside.
a.local node
b.home node
c.remote node
d.source node
80. In a directory protocol in which state no processor has a copy of the cache
block?
a.shared
b.uncached
c.exclusive
d.Invalidate
81. What is the number of bus transactions required for all n processors to acquire a
lock on a variable simultaneously, assuming they are all spinning when the lock
is released at time 0.
a.n*n
b.2n+1
c.2n
d.n2 +2n
82. Suppose there are 10 processors on a bus that each they to execute a barrier
Simultaneously . Determine the number of bus transactions required for all 10
Processors to reach the barrier, be released from the barrier and exit the barrier
a.204
b.205
c.120
d.102
83. How many bus transactions are needed to have 10 processors lock and unlock
the variable using a queuing lock that updates the lock on a miss?
a.n2 + 2n
b.(3n2 + 11n) / 2-1
c.2n+1
d.3n-1
84. The cost of building basic synchronization primitives will be too _ _ _ _ _ _ _ _ _
and will _ _ _ _ _ _ _ _ as the processor count increases
a.high,decrease
b.high,increase
c.low,decrease
d.low,increase
85. Which of the following statements is false about queuing locks
a.Can be implemented either in Hardware of Software
b.If the lock is free, it is simply returned to the processor.
c.They are used to reduce the performance of barrier operation
d.Queuing lock implementation in software assumes a bus-based multiprocessor
86. _ _ _ _ _ _ _ synchronization primitives returns the value of a memory location
and automatically increments it
a.exchange
b.test-and-set
c.fetch-and-increment
d.read-and-update
87. If multiprocessors are attempting to get the lock, each will generate the _ _ _ _
__
a.Read
b.update
c.set lock
d.write
88. _ _ _ _ _ _ _ _ _ is a common technique for reducing contention in shared
resources including access to shared networks and buses
a.Simple barrier
b.exponential back off
c.sense-reversing barrier
d.true based barrier
89. Hardware queuing locks implementation assumes a _ _ _ _ _ _ _ _
multiprocessor
a.bus-based
b.directory-based
c.message-passing
d.Distribute shared memory
90. Synchronization problems are quite acute in _ _ _ _ _ _ _ _ _ microprocessors
a.small scale
b.very small scale
c.medium scale
d.large- scale
91. SMT exploits _ _ _ _ _ _ _ _ _ _ _ parallelism on a multiple-issue superscalar and
hence it is included in _ _ _ _ _ _ _ _ _ processors targeted at server markets
a.thread-level, low end
b.thread level, high-end
c.Instruction - level, low end
d.Instruction - level, high end
92. Data cache performs slightly _ _ _ _ _ with SMT, while the l2 cache performs
slightly _ _ _ _ _ _ _ _
a.worse ,better
b.better,worse
c.better,better
d.worse,worse
93. Which of the following statement is false about fine-grained multithreading
Switches between threads on each instruction, causing the execution of multiple
threads to be interleaved
b.the CPU must be able to switch threads on every clock cycle
c.it hides the throughput losses that arise from both short and long stalls
d.it fastens the execution of the individual threads
94. _ _ _ _ _ _ _ _ _ _ provides unique register identifiers , instructions from
multiple threads can be mixed in the data path without confusing sources and
destinations across the threads
a.Register renaming
b.Register exchange
c.Register reordering
d.Register prefetch
95. _ _ _ _ _ _ _ _ _ _ _ multithreading achieves the improvement in throughput at
the cost of some overhead
a.
b.
super scalar
coarse - grained
a.
c.fine - grained
d.simultaneous
96. _ _ _ _ _ _ multithreading switches between threads on each instruction causing
the execution of multiple threads to be interleaved
a.super scalar
b.coarse - grained
c.fine - grained
d.simultaneous
97. _ _ _ _ _ _ _ multithreading uses the insight that a dynamically scheduled
processor already has many of the hardware mechanisms needed to support the
integrated exploitation of TLP through multithreading .
a.super scalar
b.coarse - grained
c.fine - grained
d.simultaneous
98. In the _ _ _ _ _ _ _ _ case the interleaving of threads eliminate fully empty slots
a.super scalar
b.coarse - grained
c.fine - grained
d.simultaneous
99. Simulation results have shown that sharing everything is key to maximizing _ _
_ _ _ _ _ _ Performance
a.super scalar
b.coarse - grained
c.fine - grained
d.simultaneous MT
100.The processor configuration for the evaluation of an SMT extension starts
with an aggressive superscalar that has roughly _ _ _ _ _ _ _ _ the capacity of
existing superscalar processors in 2001.
a.same as
b.double
c.thrice
d.ten times
101.Th advertised average seek time is 5 ms, the transfer rate is 40MB/Sec, it
rotates at 10,000 RPM and the controller overhead is 0.1ms. Assume the disk is
idle so that there is no queuing delay. What is the average time to read or write
a 512 byte sector for a disk?
a.8.01
b.8.21
c.8.11
d.8.0
102.For flash ,assume it takes 65ns to read 1 byte,1.5Fs to write 1 byte and
5ms to erase 4KB.What are the times required to read and write a 64KB block to
flash memory.
a.178.3,4.3
b.178.3,178.3
c.4.3,178.3
d.4.3,4.3
103._ _ _ _ _ _ _ _ _ _ _ device is used to handle the complexities of
disconnect / connect and read ahead in magnetic disks.
a.
b.
c.
d.
104.
a.
Disk controller
array controller
DMA controller
I/O controller
Array density is measured as _ _ _ _ _ _ _ _ _ _ _ _ _
Tracks/inch on a disk surface*(bits/inch) on a track
b.Tracks/bits on a disk surface*(bits/inch) on a track
c.Bits/inch on a disk surface*(bits/inch) on a track
d.Tracks/inch on a disk array*(bits/inch) on a track
105._ _ _ _ _ _ _ _ _ tapes limit the speed at which the tapes can spin with out
breaking or jamming.
a.
b.
c.
d.
106.
___
a.
b.
c.
d.
107.
a.
b.
c.
d.
108.
Longitudinal
near line
latitudinal
elical scan
The disk surface is divided into concentric circle, designated _ _ _ _ _ _ _ _
Tracks
sectors
platter
cylinder
Rewritable DVD drives cost _ _ _ _ _ _ times as much as DVD-ROM drives
5
10
50
100
sLow cost VCRS and camcorders make us of _ _ _ _ _ _ _ _ _ _ _ _ _ _ tapes
a.Longitudinal
b.near line
c.latitudinal
d.helical scan
109._ _ _ _ _ _ _ _ tapes mean access to terabytes of information in tens of
seconds.
a.
longitudinal
near line
latitudinal
helical scan
Storage device used for embedded applications is _ _ _ _ _ _ _ _ _
Magnetic disk
magnetic tape
flash memory
DVD
Which of the following statement is true regarding I/O bus.
They are short
high speed
Have a wide range in the data bandwidth of the devices connected to them
Do not follow a bus standard.
Which of the following is a false statement regarding the I/O processor
They facilitate simultaneous execution of several processes
They have dedicated tasks
parallelism they enable is very high
Doesn't normally change information
Which of the following statement is false
Bus serves as a shared communication link between the sub systems.
Cost of the bus is high
The maximum speed of the bus is largely limited by physical factors.
Bus creates a communication bottleneck.
Which option for a bus among the following leads to high performance.
A multiplex address and data lines
Narrower
No arbitration
d.Synchronous
115.Split-transaction bus has _ _ _ _ _ _ _ _ _ _ band width, but it usually has
_ _ _ _ _ _ _ _ _ latency than a bus that is held during the complete transaction
a.
b.
c.
d.
116.
Higher, lower
lower, higher
Higher, higher
lower, lower
Clock rate of PCI is _ _ _ _ _ _ _ _ _ _
a.10 MHz
b.20 MHz
c.33 or 66MHz
d.up to 100 MHz
117.Which of the following is a serial I/O bus often used in embedded
computers.
a.SCSI
b.PCI
c.PCI-X
d.SPI
118.In _ _ _ _ _ _ _ _ _ _ _ _ , portions of the machines address space are
assigned to I/O devices.
a.Isolated I/O
b.Memory mapped I/O
c.Programmed I/O
d.Interruptdriven
119._ _ _ _ _ _ _ _ _ _ _ _ relieves the CPU from waiting for every I/O event,
but many CPU cycles are still spent in transferring data
a.Interrupt-driver I/O
b.Programmed I/O
c.DMA
d.I/O mapped I/O
120.Au1000 includes about _ _ _ _ _ _ _ _ _ DMA channels and _ _ _ _ _ _ _ _
I/O device controllers on chip respectively.
a.
b.
c.
d.
121.
1,2
10,20
100,200
50,100
The storage overhead of RAID 6 is _ _ _ _ _ _ _ _ _ _ _ _ that of RAID 5
a.Same as
b.twice
c.thrice
d.half
122.Achieving higher _ _ _ _ _ _ _ _ _ _ requires improvement in software
quality and software fault tolerance.
a.
b.
c.
d.
123.
a.
b.
c.
d.
124.
chips
a.
Reliability
Availability
Dependability
Operability
_ _ _ _ _ _ _ _ faults exist for a limited time and are not recurring
Hard
Transient
Intermittent
Permanent
_ _ _ _ _ _ _ _ _ _ faults have declined due to a decreasing number of
in systems, reduced power, and fewer connectors
Design
126.
Operation
Environment
Hardware
Which among the following is not a fault classification in VAX systems
Hardware
Operating system
design fault
system management
_ _ _ _ _ _ _ _ _ _ automatically forces accesses to several disks.
a.seeking
b.latency
c.tracking
d.striping
127.N devices generally have _ _ _ _ _ _ _ _ _ _ the reliability of a single
device
Non redundant disk array is often called _ _ _ _ _ _ _ _ _ _ _ _ _
Raid 0
Raid 2
Raid 3
Raid 5
The distributed parity organization is _ _ _ _ _ _ _ _ _ _ _
a.Raid 0
b.Raid 3
c.Raid 4
d.Raid 5
130.A system _ _ _ _ _ _ _ _ _ occurs when the actual behavior deviates from
the specified behavior
132.
Fault
error
failure
change
Which of the following is not a characteristic of TPC bench mark.
Price is included with the benchmark results
The data size must scale in size as throughput increases
The benchmark results are not audited
An independent organization maintains the benchmarks
What is the performance metric of complex query OLTP bench mark
a.Transactions per second
b.new order transactions per minute
c.Queries per hour
d.web interactions per second
133.The work-load is gradually _ _ _ _ _ _ _ _ _ _ until the server software is
saturated with hits and the response time _ _ _ _ _ _ _ _ _ _ _ significantly
a.Increases, increases
b.increases, decreases
c.Decreases, increases
d.Decreases, decreases
134.A quad processor running IIS/Windows 2000 is _ _ _ _ _ _ _ _ _ a dual
processor running TUX/LINUX.
a.
b.
Faster than
slower than
c.same as
d.almost equal to
135._ _ _ _ _ _ reconstruction speed implies _ _ _ _ _ _ _ _ _ application
performance
a.
b.
c.
d.
136.
Increased, increased
increased, decreased
Decreased, increased
Decreased, decreased
Transaction processing is concerned with _ _ _ _ _ _ _ _ _ _
a.Data rate
b.bit rate
c.I/O rate
d.failure rate
137.What is the bench mark used for evaluating the performance of WWW
Servers
140.
__
SPECSFS
TPC
SPECWEB
SPEC89
For every 100 NFS operations per second, the capacity must increase by _
___
1GB
10GB
100GB
1000GB
Disk media failures on writes fall into which category of faults?
Transient
Intermittent
Permanent
Operation
Linux reconstructs _ _ _ _ _ _ _ _ _ and Solaris reconstructs _ _ _ _ _ _ _ _
a.Slowly, slowly
b.slowly, quickly
c.quickly, quickly
d.quickly, slowly
141.Assuming that the components lifetimes are exponentially distributed and
that failures are independent, compute the failure rate of a disk subsystem with
the following components and MTTF.
. 10 disks, each rated at 1,000,000 - hours MTTF
. 1 SCSI controller, 200,000 - hours MTTF.
. 1 power supply, 200,000 - hours MTTF
a.10/1,000,000
b.12/1,000,000
c.22/1,000,000
d.20/1,000,000
142.Assume a disk subsystem with the following components and MTTF
. 10 disks, each rated at 1,000,000 - hours MTTF
. 1 SCSI controller, 200,000 - hours MTTF.
. 1 power supply, 200,000 - hours MTTF
. 1 FAN 200,000 - hours MTTF.
. 1 SCSI cable, 1,000,000 - hours MTTF.
Compute the MTTF of the system as a whole assuming that the age of the
component is not important in probability of failure and that failures are
independent
a. 2,700,000-hours
b.2,000,000-hours
c.192,860 hours
d.43,500 hours
143.What is the response time of an I/O system with a single disk, if it gets on
average 64 I/O requests per second and the average disk service time in 7.8 ms.
a.
b.
c.
d.
144.
7.8ms
15.6ms
14ms
3.9ms
Which of the following violates rule of thumb
a.No disk should be used more than 80 % of the time
b.No disk arm should be seeking more than 60 % of the time
c.No disk string should be utilized less than 40 %
d.No I/O bus should be utilized more than 75 %
145.What is the utilization of seek time per disk, if the time of average seek in
5s with 100 IOPS
a.
b.
c.
d.
146.
100 %
50 %
25 %
1%
In which design of I/O system shows the folly of 100 % utilization
a.Response times of the naive cost-preformance design & evaluation
b.Availability if the naove cost-preformance desogn & evaluation
c.more realistic cost performance design and evaluation
d.more realistic design for availability and its evaluation
147.If the OS uses 50,000 CPU instructions for a disk I/O. What is the
maximum IOPS for CPU with 2500 MIPS?
a.50,000 IOPS
b.25,000 IOPS
c.10,000 IOPS
d.1,00,000IOPS
148.Mean-time until data loss (MTDL) increase with _ _ _ _ _ _ _ _ disk
reliability, and _ _ _ _ _ _ _ _ _ _ MTTR.
a.
b.
c.
d.
149.
__
Increased, reduced
increased, increased
reduced, reduced
reduced, increased
In Performance-tuned organization the disk utilization is _ _ _ _ _ _ _ _ _
a.100 %
b.80 %
c.70 %
d.60 %
150.What is the disk access latency for performance and availability tuned
organization
a.238ms
b.40ms
c.41ms
d.90ms
151.The loss of signal strength as it passes through a medium, called _ _ _ _ _
_ , limits the length of the fiber
a.
b.
c.
d.
Attenuation
multipart fading
signal to noise ratio
interference
152.Suppose you have 25 magnetic tapes, each containing 40GB.Assume that
you have enough tape readers to keep any network busy. How long will it take to
transmit the data over a distance of 1 Km using cat5 twisted pair wires at 100M
bits/sec.
a.
___
a.
b.
c.
d.
154.
22.8 hrs
2.3hrs
0.9hrs
0.25hrs
By limiting the length to 100 meters,``Cat5" wiring can be used for _ _ _
___
1M bits /sec
10M bits/sec
100M bits/sec
1000M bits/sec
Which of the following statement is true about single mode fiber
a.Poor transmitter
b.more reliable
c.More expensive
d.Easy to attach connectors to single mode
155.Level 3 unshielded twisted pairs was good enough for _ _ _ _ _ _ _ _ _
Ethernet
a.
d.
156.
1M bits /sec
10M bits/sec
100M bits/sec
1000M bits/sec
_ _ _ _ transmits digital data as pulses of light
a.Fiber optics
b.twisted pairs
c.base band coax
d.broad band coax
157._ _ _ _ _ _ _ _ was deployed by cable television companies to deliver a
higher rate over a few kilometers.
a.
b.
c.
d.
159.
coaxial cable
cat 5 UTP
level 3 UTP
fiber optic cable
Which among the following is a simplex media
''cat3" UTP
''cat 5" UTP
coaxial cable
fiber optics
The diameter of multimode fiber is _ _ _ _ _ _ _ _ _ _ _ _
a.8 to 9 microns
b.62.5 microns
c.100 microns
d.625 microns
160._ _ _ _ _ _ _ _ _ sends different streams simultaneously on the same fiber
using different wavelengths of light.
a.WDM
b.TDM
c.FDM
d.CDM
161.In a failure-intolerant LAN if thetotal intervals and intervals of no failures
are 8974 and 8605 respectively, then what percentages of hours a user can`t
get his work done
a.41 %
b.4.1 %
c.4.5 %
d.5%
162.If the number of failures of 58 desktop computers on a traditional LAN are
654 and that these failures are equally distributed among work stations, then
what percentage of hours a user on a workstation can't get his work done.
a.0.13 %
b.1.3 %
c.13 %
d.4.1 %
163._ _ _ _ _ _ followed open standards and have less stringent electrical
requirements.
168.
I/O buses
Memory buses
USB
network interface
Software failures occur _ _ _ _ _ _ _ _ _ than Hardware failures
Less frequently
more frequently
Equally
much more frequently
_ _ _ _ _ _ _ _ _ latency schemes sacrifice fault tolerance
low
high
moderate
very high
Memory buses provide _ _ _ _ _ _ _ bandwidth and _ _ _ _ _ _ latency
I/O buses
Higher,lower
lower,higher
lower,lower
Higher,higher
Which is the best I/O technique to send large messages?
Programmed I/O
Interrupt driven I/O
DMA
Memory-mapped I/O
Succesful standards include _ _ _ _ _ _ _ _ cost and stability
a.High
b.Low
c.Moderate
d.Very high
169.The communication system must have mechanisms for _ _ _ _ _ _ _ of a
message in case of failure
a.Recovery
b.Diversion
c.destroying
d.Retransmission
170._ _ _ _ _ _ _ _ _ _ have the ability to work around failed nodes and
switches
a.
b.
c.
d.
SANs
MANs
LANs
WANs
171.A gigabit per second LAN can fully occupy a _ _ _ _ _ _ _ _ GHZ CPU when
running TCP/IP
Which of the following is not true regarding SAN
the server is like a firewall for the SAN
graceful behavior under congestion is critical for SANS
SANs appreciate dropping packets during congestion is critical for SANS
protocol overhead in much lower for a SAN
What is the size of the smallest packet on the Ethernet
64 bytes
128 bytes
256 Bytes
512 Bytes
A SAN that tries to optimize based on shorter distance is _ _ _ _ _ _ _ _ _
Infiniband
Ethernet
ATM
Ultra band
_ _ _ _ _ _ _ _ _ _ is used for congestion control in ATM
Carrier sense
credit based
back pressure
debit based
Ethernet is codified as IEEE standard _ _ _ _ _ _ _ _ _ _ _
802.2
802.3
802.4
802.5
Bridges operate at _ _ _ _ _ _ _ _ _ _ layer of the OSI model
Physical
Data link
Network
Transport
Routers are _ _ _ _ _ _ _ _ _ _ _ than Bridges
faster
slower
of same speed
very faster
Which among the following operate at the network layer of OSI model
hubs
routers
bridges
switches
Which among the following is connection oriented
a.Ethernet
b.Infiniband
c.ATM
d.Fast Ethernet
181.Small SMP's with _ _ _ _ _ _ _ _ processors has much better cost- performance than clusters
a. 6-8
b.4-6
c.2-4
d.1-2
182._ _ _ _ _ _ _ _ server has the goal that a node can fail or be upgraded
without bringing down the whole machine.
a.SPEC WEB
b.SPECSFS
c.IBM series 300
d.Sun Fire 6800
183._ _ _ _ _ _ _ _ _ availability and _ _ _ _ _ _ _ _ _ extensibility make
clusters attractive to service provides for the WWW.
a.High, incremental
b.low, incremental
c.High, decremental
d.low, decremental
184.TPC-C cluster scale by a factor of _ _ _ _ _ _ _ _ in price or processors
while maintaining respectable cost-performance.
a.2
b.4
c.8
d.16
185.Clusters are used for the _ _ _ _ _ _ _ _ computers, NUMA the _ _ _ _ _ _ _
_ computers
a.smaller, largest
b.smaller, smaller
c.largest, smaller
d.largest, largest
186.A Sequential program in a cluster of N machines has _ _ _ _ _ _ _ _ _ _ _ _
_ the memory available compared to a sequential program in a shared memory
multiprocessor.
1/N
N times
2N times
1/(2N)
Administering a cluster of N machines is close to the cost of administering
N independent machines
a single, big machine
N/2 independent machinces
a single, small machine
Clusters are usually connected using the _ _ _ _ _ _ _ _ of the computer
Memory bus
I/O bus
Network interface
USB
Clusters gets _ _ _ _ _ _ _ _ performance by scaling.
low
high
moderate
very low
Memory bus has _ _ _ _ _ _ _ bandwidth and _ _ _ _ _ _ _ latency.
lower, lower
higher, higher
igher, lower
d.lower, higher
191.Astandard VME rack is _ _ _ _ _ _ _ _ _ inches wide and about _ _ _ _ _ _ _
_ feet tall, with a typical depth of _ _ _ _ _ _ _ _ _ _ inches respectively.
a.6,19,30
b.30,6,19
c.19,30,6
d.19,6,30
192.Which design cluster example includes the cost of software, the cost of
space, some maintenance costs and operator costs.
a.Cost of cluster hardware alternatives with local disk
b.Cost of cluster hardware alternatives with disk over SAN
c.Cost of cluster options that in more realistic
d.Cost of performance of a cluster for transaction processing
193.The uniprocessor clusters costs _ _ _ _ _ _ times the two-way SMP option,
and the 8 way SMP cluster costs _ _ _ _ _ _ _ _ _ _ times the two way SMP.
a.
b.
c.
d.
194.
1.6, 1.1
1.1, 1.6
1,6
1,1
IBM RAID controller requires _ _ _ _ _ _ _ _ _ _ disk.
a.SCSI
b.IDE/ATA
c.RAMAC
d.FC-AL
195.Smaller computers are generally _ _ _ _ and _ _ _ _ _ _ _ for a given
function compared to the larger computers.
a.
b.
c.
d.
196.
Costlier, Slower
Cheaper, Slower
Cheaper , faster
costlier, faster
What is the size of L2 Cache in xseries370?
a.256kB
b.512kB
c.1024kB
d.2048kB
197.The database cost is primarily a _ _ _ _ _ _ _ _ _ _ function of the number
of processors.
a.non-linear
b.linear
c.ramp
d.step
198. FC-AL can be connected in a loop with up to _ _ _ _ _ devices.
a.126
b.127
c.128
d.129
199. Collaction rates are _ _ _ _ _ _ _ per unit as space requirements increases
a.costier
b.moderate
c.cheaper
d.much cheaper
200. Collaction Sites are designed assuming no more than _ _ _ _ watts per square
foot.
a.
b.
1
10
c.
d.
100
1000

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